1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the adjustment of characteristics of individual field effect transistor elements by providing an asymmetric transistor architecture.
2. Description of the Related Art
Integrated circuits typically include a large number of individual circuit elements, such as transistors, capacitors, resistors and the like. These individual circuit elements are electrically connected according to the desired circuit layout by respective conductive lines, which are mainly formed in separate “wiring” layers that are typically referred to as metallization layers. For enhancing the performance of the integrated circuit, usually the number of individual circuit elements is increased, thereby obtaining a more complex functionality of the circuit, and associated therewith the feature sizes of the individual circuit elements are reduced, thereby enhancing performance of the individual circuit elements, in particular of the transistors, which represent the dominant components in complex circuits. Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, MOS technology is presently the most promising approach due to the superior characteristics in view of operating speed, manufacturing costs and/or power consumption. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed in and on an appropriate crystalline semiconductor material, wherein, currently, the vast majority of logic circuitry is fabricated on the basis of silicon. Typically, a MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed at an interface of highly doped drain and source regions with a channel region disposed between the drain region and the source region, wherein the channel region is inversely or weakly doped with respect to the drain and source regions. The conductivity of the channel region, which represents an essential device criterion as the reduced current drive capability of scaled devices with reduced transistor width has, at least partially, to be compensated for by an increased conductivity, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on the dopant concentration, the mobility of the charge carriers and, for a transistor width, the distance between the source and drain regions, which is also referred to as channel length. In addition to the conductivity of the channel region in the saturated state and the linear operating state of the transistor, performance is also significantly influenced by the transistor's capability of rapidly creating a conductive channel in the channel region upon application of a specified control voltage to the gate electrode, since usually the transistors are operated in a switched mode requiring a fast transition from the transistor on-state to the transistor off-state and vice versa. Moreover, other aspects also have to be taken into consideration when designing a transistor of high performance circuit. For instance, static and dynamic leakage currents may significantly affect the overall performance of an integrated circuit, as the achievable amount of heat dissipation that is required for transistor architectures producing high dynamic and/or static leakage currents may restrict the maximum practical operating frequency.
Furthermore, sophisticated lateral and vertical dopant profiles may be required in the drain and source regions to maintain controllability of the channel region for a channel length of approximately 50 nm and significantly less, as is typically applied in modern transistor elements. As is well known, short channel effects may require a reduction of the thickness of the gate insulation layer which, however, may no longer be a viable option on the basis of silicon dioxide since, at a thickness of approximately 1 nm, significant leakage currents may occur, as explained above. Appropriate design countermeasures, on the other hand, may be accompanied by a reduction of channel conductivity, which has resulted in advanced strain engineering techniques for creating a desired type of strain in the channel region which may enhance charge carrier mobility therein. For example, for a standard crystallographic orientation of a silicon layer, i.e., a (100) surface orientation with the channel length directed along a <110> crystal axis, creating a tensile strain along the channel length direction may significantly enhance electron mobility, which thus leads to increased drive current capability of an NMOS transistor. Thus, a plurality of interdependent factors may finally determine the overall transistor characteristics, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a transistor element 100 at an early manufacturing stage. As illustrated, the transistor element 100 comprises a substrate 101, above which is formed a silicon-based semiconductor layer 102. The semiconductor layer 102 and the substrate 101 may be separated by a buried insulating layer 103, thereby providing a silicon-on-insulator (SOI) configuration. An SOI transistor architecture may have certain advantages relative to a “bulk” configuration in which the semiconductor layer 102 may represent an upper portion of a substantially crystalline substrate material so that electrical isolation between different transistors may require corresponding deep well regions and the like. On the other hand, in an SOI configuration, the buried insulating layer 103 may provide the vertical insulation, while appropriate isolation structures, such as shallow trench isolations (not shown), may laterally enclose the transistor 100, thereby laterally insulating the transistor 100 from neighboring circuit elements. For instance, by appropriately designing respective drain and source regions, the junction capacitance of the corresponding PN junctions may be reduced compared to bulk devices, thereby also providing enhanced operating speed. Furthermore, in the manufacturing stage shown, a gate electrode structure 104 is formed on the semiconductor layer 102 and comprises a gate insulation layer 104A, separating a gate electrode 104B from a portion of the semiconductor layer 102, which may be referred to as channel region 102A. The gate electrode structure 104 further comprises a dielectric material or spacer elements 104C formed on sidewalls of the gate electrode 104B.
The transistor 100 as shown in FIG. 1a may be formed on the basis of the following well-established process techniques. The semiconductor layer 102 may be formed on the buried insulating layer 103 on the basis of well-established techniques, such as wafer bond processes and the like. Thereafter, photolithography, etch and deposition processes may be performed to define the lateral dimensions of an active region within the semiconductor layer 102 for the transistor 100 by providing appropriate isolation structures, as previously explained. Thereafter, implantation processes may be performed to position one or more dopants within the semiconductor layer 102 to thereby form a specified vertical dopant profile (not shown) according to the transistor characteristics of the device 100, which may finally result in a specified vertical dopant profile in the channel region 102A. Next, material layers for the gate insulation layer 104A and the gate electrode 104B may be formed, for instance, by advanced oxidation and/or deposition techniques for the gate insulation material and by advanced low pressure chemical vapor deposition (CVD), if a polycrystalline silicon material is used. Thereafter, highly sophisticated lithography and etch techniques may be employed to pattern the gate electrode material and the gate dielectric material to form the gate electrode 104B and the gate insulation layer 104A on the basis of a desired design gate length, which may be 50 nm and less in sophisticated applications. Subsequently, a complex implantation sequence may be performed to prepare the semiconductor layer 102 for establishing a desired vertical and lateral dopant profile adjacent to the channel region 102A. For this purpose, a so-called pre-amorphization implantation process 105 is performed during which a non-doping ion species, such as germanium and the like, may be implanted into the semiconductor layer 102 so as to substantially completely destroy the crystalline lattice structure down to a specified depth, thereby forming substantially amorphized regions 106. During the implantation process 105, the process parameters, such as implantation energy for the species under consideration and the ion beam current, may be adjusted to obtain sufficient lattice damage in the region 106, which may reduce channeling effects during a subsequent implantation process and which may also enhance the re-crystallization and activation of dopant atoms. Thereafter, the further processing may be continued by introducing dopant species in order to define respective drain and source regions and the corresponding lateral and vertical shape and the respective dopant gradients at the PN junctions. For example, a dopant species generating the same conductivity type as the basic doping in the semiconductor layer 102 may be introduced by any appropriate implantation techniques, possibly by using a tilt angle in order to form so-called halo regions (not shown) to enable an adjustment of the dopant gradient in combination with a dopant species of opposite conductivity type that may be introduced for forming drain and source regions.
FIG. 1b schematically illustrates the device 100 in a substantially completed manufacturing state. Thus, the device 100 may comprise a source region 108, which may include an extension region 108E, i.e., a shallow doped region connecting to the channel region 102A, thereby defining a PN junction with this region, when enrichment type transistors are considered. In the example shown, the transistor 100 may be assumed to represent an N-channel transistor so that the channel region 102A may be lightly P-doped, while the source region 108 and a drain region 107 are heavily N-doped. As illustrated, the drain region 107 may also include an extension region 107E which may have a symmetric configuration with respect to a lateral offset or overlap with respect to the gate electrode 104B. In this case, the terms drain and source may be interchangeable and may be defined by respective voltages supplied to the transistor 100 during operation. Furthermore, the source and drain regions 108, 107 may comprise deeper portions 108D, 107D which may extend down to the buried insulating layer 103, thereby providing a reduced junction capacitance, as previously explained. In the manufacturing stage shown, the drain and source regions 107, 108 may be in a substantially crystalline state so that the previously created substantially amorphized portions 106 are re-grown in a substantially crystalline state. Furthermore, the device 100 may comprise a spacer structure 109 which may include one or more individual spacer elements 109A, 109B, possibly in combination with respective etch stop materials 109C, 109D. For example, the spacer elements 109A, 109B may be comprised of silicon nitride, while the etch stop liners 109C, 109D, if provided, may be comprised of silicon dioxide. Furthermore, the gate electrode structure 104 may comprise a metal silicide region 104D, which may be formed commonly with metal silicide regions 110 provided in the drain and source regions 107, 108.
The extension regions 107E, 108E may be formed by an ion implantation process within the substantially amorphized regions 106, as previously explained, possibly in combination with respective halo implantation processes so as to obtain the desired dopant gradient. Thereafter, in some manufacturing strategies, the device 100 may be annealed to activate the dopants in the extension regions 107E, 108E, while, in other cases, the process may be continued by forming the spacer structure 109, or at least a portion thereof. For example, the etch stop liner 109C may be deposited, followed by the deposition of a silicon nitride material, which may subsequently be patterned in order to obtain the spacer element 109A. Using the gate electrode structure 104 and the spacer element 109A as an implantation mask, a further portion of the deep drain and source regions 107D, 108D may be formed on the basis of appropriately set implantation parameters. Thereafter, the spacer element 109B may be formed, possibly using the etch stop liner 109D, and a further portion of the deep drain and source regions 107D, 108D may be provided by ion implantation. Next, the device 100 may be annealed to activate the dopant introduced by the preceding implantation sequences, thereby placing a high amount of dopant atoms at lattice sites, while also substantially re-crystallizing implantation-induced lattice damage. For example, if the anneal process may represent the first anneal process of the manufacturing sequence, the extension regions 107E, 108E may also be activated and the previously substantially amorphized regions 106 may be re-crystallized. During the anneal process, a desired final lateral offset or overlap of the extension regions 107E, 108E with the gate electrode 104B may be adjusted, while the vertical dopant concentration may be driven down to the buried insulating layer 103. That is, during the anneal cycle, thermally induced diffusion of the dopants occurs in accordance with the respective concentration gradient of the dopant species under consideration, thereby substantially determining the finally obtained size and characteristics of the drain and source regions 107, 108. Thereafter, the manufacturing process may be continued with the formation of the metal silicide regions 110, 104D which may be accomplished by depositing a refractory metal and initiating a chemical reaction with the underlying silicon material. Subsequently, an interlayer dielectric material may be formed and respective contacts may be provided to provide electrical connections to the drain and source regions 107, 108 and the gate electrode structure 104. For convenience, these components are not shown in FIG. 1b. 
During operation of the device 100, typically, a supply voltage is applied to the drain region 107 and the source region 108, for example approximately 1.5-5.0 volts for typical CPUs, while a corresponding control voltage is applied to the gate electrode 104B in order to define the status of the channel region 102A. For an N-channel enhancement transistor, upon application of a control voltage to the gate electrode 104B below a specified threshold voltage which is determined, among other things, by the vertical dopant profile within the channel region 102A, the transistor 100 is in an off-state, that is, the channel region 102A is not conductive and one of the PN junctions is reversed bias. However, during the off-state, the moderately high electrical field prevailing at the drain side, and in particular at the overlap between the extension region 107E and the gate electrode 104B, may lead to tunnel currents into the gate electrode 104B, especially when the gate insulation layer 104A has a thickness of approximately 2 nm and less. These currents may be considered as static leakage currents and may significantly contribute to overall power consumption in sophisticated devices. Moreover, the extension region 107E and the gate electrode 104B may define a capacitor which has to be charged and discharged when operating the transistor 100 in a switched mode, wherein the transistor 100 may also transit through a linear operating mode in which the drain current may be substantially proportional to the effective gate voltage that is determined by the charge state of the corresponding parasitic capacitor.
When applying a control voltage that is above the threshold voltage, a conductive channel is formed in the channel region 102A originating from the source extension region 108E and terminating at the drain extension region 107E. For building up a conductive channel, in the present case created by electrons, an overlap at the source side and a steep concentration gradient at the source side may be advantageous in obtaining a high drive current. However, the steep concentration gradient at the drain side may result in increased creation of electron hole pairs, thereby increasingly creating holes at the body region of the transistor 100, i.e., in the region between the deep drain and source regions 107D, 108D. The accumulated charge carriers may have to be discharged, thereby also contributing to increased dynamic leakage currents. Moreover, during the formation of the conductive channel, the parasitic capacitance caused by the overlapping extension regions 107E, 108E may require high currents for recharging the parasitic capacitor and may thus delay the start of the on-state so that, during the substantially linear operating mode, when charging the parasitic capacitor, a moderately high on resistance may be observed in the transistor 100.
For this reason, asymmetric transistor configurations with respect to the drain and source regions have been proposed, for instance, by providing a certain offset between the drain extension region 107E and the gate electrode 104B in order to enhance overall transistor performance.
Typically, the asymmetric transistor configuration may be obtained on the basis of a tilted implantation process in order to introduce the dopant species for the extension regions 107E differently at the drain side and the source side of the transistor, for instance so as to obtain an increased overlap at the source side of the transistor to provide enhanced charge carrier injection, while a reduced overlap or even a certain offset at the drain side may provide a reduced vertical electric field strength, thereby reducing hot carrier injection. Although the provision of an asymmetric transistor configuration may be a promising approach for enhancing overall transistor performance for given critical dimensions, it turns out that the potential of appropriately designing the drain and source regions, i.e., the corresponding dopant profiles, may not fully be taken advantage of on the basis of conventionally used tilted implantation techniques.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.